Liquid crystal display devices (LCDs) characterized by their thin design, light weight and low power consumption have come into widespread use in recent years and are utilized in the display units of mobile devices such as portable telephones (mobile telephones or cellular telephones), PDAs (Personal Digital Assistants) and laptop personal computers. Recently, however, liquid crystal display devices have come to be provided with large-size screens and techniques for dealing with moving pictures have become more advanced, thus making it possible to realize not only mobile applications but also stay-at-home large-screen display devices and large-screen liquid crystal televisions. Liquid crystal display devices of an active matrix driving system which is capable of presenting a high-definition display are being utilized as these liquid crystal displays devices.
The typical configuration of an active-matrix liquid crystal display device will be described with reference to FIG. 11. The principal components connected to one pixel of a liquid crystal display unit are illustrated schematically by equivalent circuits in FIG. 11.
In general, a display unit 960 of an active-matrix liquid crystal display device comprises a semiconductor substrate on which transparent pixel electrodes 964 and thin-film transistors (TFTs) 963 are laid out in the form of a matrix (e.g., 1280×3 pixel columns×1024 pixels rows in the case of a color SXGA panel); an opposing substrate on the entire surface of which a single transparent electrode 967 is formed; and a liquid crystal material sealed between these two substrates arranged to oppose each other. The liquid crystal has capacitance and forms a capacitor 965 between the pixel electrodes 964 and electrode 967. Further, an auxiliary capacitor 966 for assisting the capacitance of the liquid crystal is provided.
In the above-described liquid crystal display device, the TFT 963, which has a switching function, is turned on and off under the control of a scan signal. When the TFT 963 is on, a grayscale signal voltage that corresponds to a video data signal is applied to the pixel electrode 964, and the transmittance of the liquid crystal changes owing to a potential difference between each pixel electrode 964 and opposing-substrate electrode 967. This potential difference is held by the liquid crystal capacitance 965 and auxiliary capacitor 966 for a fixed period of time even after the TFT 963 is turned off, as a result of which an image is displayed.
Data lines 962 that send a plurality of level voltages (grayscale signal voltages) applied to pixel electrodes 964 and scan lines 961 that send the scan signal are wired on the semiconductor substrate in the form of a grid (the data lines are 1280×3 in number and the scan lines are 1024 in number in the case of the above-mentioned color SXGA panel). The scan line 961 and data line 962 constitute a large capacitive load owing to the capacitance produced at the intersection of these lines and capacitance, etc., of the liquid crystal sandwiched between the opposing-substrate electrodes.
It should be noted that the scan signal is supplied to the scan line 961 by a gate driver 970, and that the supply of grayscale signal voltage to each pixel electrode 964 is performed by a data driver 980 via the data line 962. Further, the gate driver 970 and data driver 980 are controlled by a display controller (not shown), a required clock CLK, control signals and power-supply voltage, etc., are supplied from the display controller, and video data is supplied from the display controller 940 to the data driver 980. At the present time, video is principally digital data.
Rewriting of one screen of data is carried out over one frame ( 1/60 of a second), data is selected successively every pixel row (every line) by each scan line, and a grayscale signal voltage is supplied from each data line within the selection interval.
Although the gate driver 970 need only supply at least a bi-level scan signal, it is required that the data driver 980 drive the data lines by grayscale signal voltages of multiple levels that conform to the number of gray levels of the grayscale. To this end, the data driver 980 has a digital-to-analog converter (DAC) comprising a decoder for converting video data to a grayscale signal voltage and an operational amplifier for amplifying the grayscale signal voltage and outputting the amplified signal to the data line 962.
Progress is being made in raising the image quality (increasing the number of colors) in mobile telephone terminals, notebook personal computers, monitors and liquid crystal TV, etc. There is now growing demand for video data of at least six bits per each of R, G, B (260,000 colors) and even eight bits or more per each of R, G, B (26,800,000 colors). For this reason, a data driver that outputs a grayscale signal voltage corresponding to multiple-bit video data is required to provide a highly accurate output voltage conforming to the gray level along with a multiple-level grayscale voltage output.
In order to prevent degradation of the liquid crystal, the data driver is such that AC drive in which positive and negative voltages are applied alternatingly is performed with respect to voltage VCOM (see FIG. 11) of the opposing substrate electrode of the liquid crystal panel. The data driver therefore outputs grayscale voltage signals for positive-polarity and negative-polarity drive.
FIG. 12A is a diagram illustrating the relationship between applied voltage and transmittance in normally white liquid crystal. FIG. 12B is a diagram illustrating the relationship between grayscale levels of a liquid crystal device that drives liquid crystal having the characteristic of FIG. 12A and the output voltage of a data driver (voltage applied to the liquid crystal). With normally white liquid crystal, the transmittance of the liquid crystal declines as the voltage applied to the liquid crystal is increased. The output voltage of the data driver in case of positive polarity drive ranges from VCOM, which corresponds to the grayscale level 255 (eight bits), to high-side power-supply voltage VDD corresponding to grayscale level 0. In case of negative polarity drive, the output voltage of the data driver ranges from VCOM corresponding to level 255 to low-side power-supply voltage VSS corresponding to grayscale level 0. It is required that the data driver provide a highly accurate voltage output over the negative and positive-polarity output voltage range VSS to VDD.
FIG. 13 is a diagram illustrating the typical configuration of a differential amplifying circuit having a positive-polarity drive amplifier and a negative-polarity drive amplifier. As shown in FIG. 13, the differential amplifying circuit includes a changeover switch SW91 for switching an input terminal Vin between the input of a positive-polarity drive amplifier 910 and the input of a negative-polarity drive amplifier 920, and a changeover switch SW92 for switching an output terminal Vout between the output of the positive-polarity drive amplifier 910 and the output of the negative-polarity drive amplifier 920.
The positive-polarity drive amplifier 910 includes N-channel MOS transistors (referred to as “NMOS transistors”) MN91 and MN92 having their sources coupled together and constructing a first differential pair; a constant current source I91 connected between the coupled sources of the NMOS transistors MN91 and MN92 and low-side power supply VSS; and P-channel MOS transistors (referred to as “PMOS transistors”) MP93 and MP94 connected between drains of the NMOS transistors MN91 and MN92 and high-side power supply VDD and constructing a current mirror. The gates (a pair of inputs) of the NMOS transistors MN91 and MN92 are connected to the changeover switch SW92 on the output side and to the changeover switch SW91 on the input side, respectively.
The negative-polarity drive amplifier 920 includes PMOS transistors MP91 and MP92 having their sources coupled together and constructing a second differential pair; a constant current source I92 connected between the coupled sources of the PMOS transistors MP91 and MP92 and high-side power supply VDD; and NMOS transistors MN93 and MN94 connected between drains of the PMOS transistors MP91 and MP92 and low-side power supply VSS and constructing a current mirror. The gates (a pair of inputs) of the PMOS transistors MP91 and MP92 are connected to the changeover switch SW92 on the output side and to the changeover switch SW91 on the input side, respectively.
In AC drive for applying positive and negative voltages alternatingly with respect to voltage VCOM of the opposing substrate electrode (see 967 in FIG. 11), the positive-polarity drive amplifier 910 and negative-polarity drive amplifier 920 are connected between the input terminal Vin and output terminal Vout alternatingly, thereby driving the data lines of the liquid crystal display panel.
However, when drive is performed separately by the positive-polarity drive amplifier 910 and negative-polarity drive amplifier 920 in positive-polarity and negative-polarity AC drive, as in the circuit arrangement illustrated in FIG. 13, a variation in the characteristics of the transistors causes an increase in a deviation (referred to as “amplitude-difference deviation”) between the driver outputs which is the difference in amplitudes between the positive-polarity output and negative-polarity output at the same grayscale level. Consequently, luminance unevenness, etc., occurs in the panel surface and image quality declines. This problem will be described below with reference to FIG. 9.
When viewed in terms of one cycle of positive-polarity and negative-polarity AC drive, luminance will take on a value approximately the same as the expected value if the amplitude difference between the positive-polarity and negative-polarity outputs at the same grayscale level does not change [see (A) of FIG. 9]. That is, if the deviation between the driver outputs which is the difference in amplitudes between the positive-polarity output and negative-polarity output at the same grayscale level is small, luminance at the same grayscale level will be uniform over the surface of the panel and the image quality will be high.
On the other hand, if the amplitude-difference deviation is large, the luminances of the positive-polarity output and negative-polarity output at the same grayscale level develop a variation on the panel surface and image quality declines.
At (B) and (C) of FIG. 9, the directions of an offset (output offset voltage) on positive and negative sides are the same. If the value of the offset is represented by ΔV, the average luminance of one cycle will be the same as the expected value [(A) of FIG. 9]. That is, in case of (B) of FIG. 9, since the offset voltage ΔV on the positive side is a positive value and the potential difference between the positive-polarity output and VCOM increases, there is a rise in luminance. On the negative side, however, since the offset voltage ΔV is a positive value and the potential difference between the negative-polarity output and VCOM decreases, there is a decline in luminance. As a result, the average luminance of one cycle is the same as the expected value because the positive and negative sides cancel each other out.
By contrast, at (D) and (E) of FIG. 9, the directions of the offset on the positive and negative sides are opposite. Consequently, the average luminance of one cycle rises in (D) and declines in (E) in comparison with the expected value. This causes luminance unevenness. More specifically, in case of (D) of FIG. 9, the offset voltage ΔV on the positive side is a positive value and there is a rise in luminance, and the offset voltage ΔV on the negative side is a negative value and there is a rise in luminance; hence, the average luminance of one cycle rises. In case of (E) of FIG. 9, the offset voltage ΔV on the positive side is a negative value and there is a decline in luminance, and the offset voltage ΔV on the negative side is a positive value and there is a decline in luminance; hence, the average luminance of one cycle declines.
Since the differential amplifying circuit described with reference to FIG. 13 is driven by amplifiers of different polarities, namely positive and negative, the direction of the offset ΔV will not necessarily be the same in the positive- and negative-polarity drive amplifiers. This means that the states illustrated at (D) and (E) of FIG. 9 may occur.
FIG. 14 is a diagram illustrating the circuit arrangement of a conventional differential amplifier disclosed in Patent Document 1, which is cited below. As shown in FIG. 14, the differential amplifier can be considered upon being divided into an input stage 810, intermediate stage 820 and final stage 830.
The input stage 810 includes PMOS transistors MP80, MP81 and MP82 and NMOS transistors MN80, NMN81 and MN82.
The intermediate stage 820 includes PMOS transistors MP83, MP84, MP85, MP86, MP87 and MP88 and NMOS transistors MN83, NMN84, MN85, MN86, MN87 and MN88.
The final stage 830 includes a PMOS transistor MP89 and an NMOS transistor MN89.
The amplifier further includes phase compensating capacitors C81 and C82 between the intermediate stage 820 and the final stage 830.
The PMOS transistors MP81 and MP82 have their sources coupled together and construct a P-channel differential pair. The PMOS transistor MP80 is connected between this P-channel differential pair and a positive power supply VDD. The PMOS transistor MP80 has a source connected to the positive power supply VDD, a drain connected to the coupled sources of PMOS transistors MP81 and MP82 and a gate connected to a constant voltage source terminal BP81. The PMOS transistor MP80 acts as a constant current source.
The NMOS transistors MN81 and MN82 have their sources coupled together and construct an N-channel differential pair. The NMOS transistor MN80 is connected between this N-channel differential pair and a negative power supply VSS. The NMOS transistor MN80 has a source connected to the negative power supply VSS, a drain connected to the coupled sources of NMOS transistors MN81 and MN82 and a gate connected to a constant voltage source terminal BN81. The NMOS transistor MN80 acts as a constant current source.
The gate of the PMOS transistor MP81 and the gate of the NMOS transistor MN81 are connected to an input terminal INN. The gate of the PMOS transistor MP82 and the gate of the NMOS transistor MN82 are connected to an input terminal INP.
The drain of the PMOS transistor MP81 is connected to a node C of connection between the drain of the NMOS transistor MN83 and the source of the NMOS transistor MN85 in the intermediate stage 820.
The drain of the PMOS transistor MP82 is connected to a node D of connection between the drain of the NMOS transistor MN84 and the source of the NMOS transistor MN86.
The drain of the NMOS transistor MN81 is connected to a node A of connection between the drain of the PMOS transistor MP83 and the source of the PMOS transistor MP85.
The drain of the NMOS transistor MN82 is connected to a node B of connection between the drain of the PMOS transistor MP84 and the source of the PMOS transistor MP86.
The PMOS transistors MP83 and MP84 have their sources coupled together and their gates coupled together, and the coupled sources are connected to the positive power supply VDD. The drains of the PMOS transistors MP83 and MP84 are connected to the nodes A and B, respectively.
The PMOS transistor MP85 has its source connected to the node A and its drain connected to the coupled gates of the PMOS transistors MP83 and MP84, the source of the PMOS transistor MP87 and the drain of the NMOS transistor MN87.
The PMOS transistor MP86 has its source connected to the node B and its drain to the source of PMOS transistor MP88, the drain of NMOS transistor MN88 and the gate of the PMOS transistor MP89.
The gates of the PMOS transistors MP85 and MP86 are coupled together and connected to a constant voltage source terminal BP82.
The NMOS transistors MN83 and MN84 have their sources coupled together and their gates coupled together, and the coupled sources are connected to the negative power supply VSS.
The drains of the NMOS transistors MN83 and MN84 are connected to the nodes C and D, respectively.
The NMOS transistor MN85 has its source connected to the node C and its drain connected to the coupled gates of the NMOS transistors MN83 and MN84, the source of the NMOS transistor MN87 and the drain of the PMOS transistor MP87. The NMOS transistor MN86 has its source connected to the node D and its drain connected to the source of the NMOS transistor MN88, the drain of the PMOS transistor MP88 and the gate of the NMOS transistor MN89. The gates of the NMOS transistors MN85 and MN86 are coupled together and connected to a constant voltage source terminal BN82.
The PMOS transistor MP87 has its gate connected to a constant voltage source terminal BP83, it source connected to the drain of the PMOS transistor MP85 and its drain connected to the drain of the NMOS transistor MN85.
The NMOS transistor MN87 has its gate connected to a constant voltage source terminal BN83, its source connected to the drain of the NMOS transistor MN85 and its drain connected to the drain of the PMOS transistor MP85.
The PMOS transistor MP87 and NMOS transistor MN87 act as floating constant current sources.
The PMOS transistor MP88 has its gate connected to a constant voltage source terminal BP84, its source connected to the drain of the PMOS transistor MP86 and its drain connected to the drain of the NMOS transistor MN86.
The NMOS transistor MN88 has its gate connected to a constant voltage source terminal BN84, its source connected to the drain of the NMOS transistor MN86 and its drain connected to the drain of the PMOS transistor MP86.
The PMOS transistor MP88 and NMOS transistor MN88 act as floating constant current sources.
The PMOS transistor MP89 is an output transistor having a source connected to the positive power supply VDD, a gate connected to the source of the PMOS transistor MP88 and a drain connected to the output terminal OUT.
The NMOS transistor MN89 is an output transistor having a source connected to the negative power supply VSS, a gate connected to the source of the NMOS transistor MN88 and a drain connected to the output terminal OUT.
The phase compensating capacitor C81 has a first end connected to the node B and a second terminal connected to the output terminal OUT. The phase compensating capacitor C82 has a first end connected to the node D and a second terminal connected to the output terminal OUT.
The differential amplifier illustrated in FIG. 14 is a so-called “rail-to-rail amplifier” (a full-range amplifier). The input stage 810 is a differential stage obtained by bundling the PMOS-transistor differential pair and the NMOS-transistor differential pair in order to implement the rail-to-rail capability. Accordingly, it is necessary to couple the outputs of the PMOS-transistor differential pair and the outputs of the NMOS-transistor differential pair.
The outputs of the differential stage, therefore, are connected to the nodes A, B, C and D of a so-called folded-cascode connection. By virtue of this connection, the outputs of the PMOS-transistor differential pair and NMOS-transistor differential pair are coupled in terms of current.
According to this arrangement, the NMOS-transistor differential pair operates within an input-signal voltage range in which the PMOS-transistor differential pair does not operate.
Conversely, the PMOS-transistor differential pair operates within an input-signal voltage range in which the NMOS-transistor differential pair does not operate. As a result, it is possible to obtain an input stage that operates in the full input range of power supply voltages.
[Patent Document 1] Japanese Patent Kokai Publication No. JP-A-6-326529 (FIG. 1)
[Patent Document 2] Japanese Patent Kokai Publication No. JP-P2001-34234A (FIG. 5)
[Patent Document 3] Japanese Patent Kokai Publication No. JP-P2002-43944A (FIGS. 2 and 3)
[Patent Document 4] Japanese Patent Kokai Publication No. JP-P2005-130332A (FIGS. 1 and 26)
The conventional differential amplifying circuit described above with reference to FIGS. 13 and 14 has a certain problem, which is set forth below. The description of this problem is based upon the results of analysis by the present inventor.
FIG. 10A is a diagram useful in describing the amplitude-difference deviation (the deviation between the driver outputs which is the difference in amplitudes between the positive-polarity output and negative-polarity output at the same grayscale level) of a data driver that uses the circuit of FIG. 13 as an output buffer. If the positive-polarity side and negative-polarity side are driven by separate amplifiers (see FIG. 13) in each output buffer, each driver output will take on any of the states shown at (B) to (E) of FIG. 9 owing to a variation in the characteristics of the transistors.
The amplitude-difference deviation therefore is very large across all grayscale levels. This means that luminance will vary (in display of the same grayscale level) across the surface of the panel (from data line to data line).
FIG. 10B is a diagram useful in describing the amplitude-difference deviation of a data driver that uses the circuit of FIG. 14 as an output buffer. If the positive-polarity side and negative-polarity side both are driven by a rail-to-rail amplifier in each output buffer, then, even though there is a variation in the transistor characteristics, the only states obtained are those at (B) and (C) of FIG. 9 in which the directions of positive-polarity and negative-polarity offsets agree owing to interaction between the P- and N-channel differential pairs in the grayscale region in which the P- and N-channel differential pairs both operate.
Consequently, there is little amplitude-difference deviation and image quality is excellent except near the grayscale level of 0.
However, in the vicinity of the 0 grayscale level, e.g., in a case where the voltage of the input signal is near VDD, the PMOS differential pair (MP81, MP82) turns off. On the other hand, in a case where the voltage of the input signal is near VSS, the NMOS differential pair (MN81, MN82) turns off. As a consequence, interaction between the PMOS differential pair and NMOS differential pair does not occur and the arbitrary states shown at (B) to (E) of FIG. 9 are the result. The result is a large amplitude-difference deviation in the vicinity of the 0 grayscale level [see FIG. 10B]. Even in the circuit of FIG. 14, therefore, luminance becomes non-uniform across the panel surface when a display near the 0 grayscale level is presented.
Although the case described above is one in which a normally white liquid crystal is driven, a similar problem occurs even in a case where a normally black liquid crystal is driven. That is, with a normally black liquid crystal, the characteristics of normally white liquid crystal shown in FIGS. 12A and 12B are reversed and the transmittance of the liquid crystal rises as the voltage applied to the liquid crystal is increased. Further, the driver for driving a normally black liquid crystal delivers a voltage output in the vicinity of the power-supply voltages VDD and VSS near the maximum grayscale level (255). Accordingly, there is a need to realize a differential amplifying circuit that suppresses amplitude-difference deviation over the full range of grayscale levels even in the vicinity of the power-supply voltages.